![]() VHDL Code for shift register can be categorised in serial in serial out shift register, serial in parallel out shift register, parallel in parallel out shift register and parallel in serial out shift register. The following code models a four-bit parallel in shift left register with load and shift enable signal. Bit serial shift in and shift out register without enable signal.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |